1. Field of the Invention
The present invention relates generally to programmable chips, and more particularly to floorplanning and placement of field programmable integrated circuits (ICs).
2. Description of Related Art
Field programmable gate arrays (FPGAs) are often selected by designers to provide a flexible approach in programming and re-programming integrated circuits in order to accommodate a system specification, correct errors in the system, or make improvements to the system by reprogramming the field programmable gate array. One conventional field programmable gate array architecture is implemented using groups of look-up tables and programmable interconnect circuits. While the look-up tables and sequential elements are connected to each other, the connections to the groups of look-up tables typically originate from a switchbox located in each group of the look-up table. A hierarchical interconnect structure connects to elements in a look-up table through a switchbox, thereby serving as the primary source of connecting look-up tables from one logic block to another logic block. The inputs to the look-up tables are therefore generated primarily from the switch box. The look-up table outputs are directly fed to other look-up tables as well as the elements within the look-up tables, but the connections to other look-up tables' inputs are made through the switch box.
Although field programmable gate arrays enable user programming of integrated circuits, these integrated circuits typically produce slower performance (clock speed) because of the delays through the transistors, switches or multiplexers used to program the interconnects between configurable logic elements. Each logic element can be connected to a multitude of other logic elements through switches in which the path from one programmable logic element to the next may be strewn with many switches, slowing down circuit operation. Some paths in a programmable IC are not as critical as others. Therefore, a customized programmable IC can be designed such that speed in the critical paths are optimized over other non-critical paths.
Routing elements have increasingly been added to programmable logic devices/ICs so that routing elements now typically occupy a much larger area than the configurable logic elements themselves. Adding to the problem is the fact that routing delays are typically much greater than logic delays, resulting in a slow operating clock frequency. In a conventional implementation, a large fraction of the routing elements may be redundant.
As semiconductor process advances into deep sub-micron regime, the cost of manufacturing a complex Application-Specific Integrated-Circuit (ASIC) chip using the state-of-art technology is sky-rocketing. As a viable solution to reduce cost, shorten product development cycle while minimizing production risk, field programmable gate array has been gaining acceptance in various applications than ever before. Traditional homogeneous field programmable gate array is mainly based on programmable Look-Up Tables (LUTs). Its logic density and performance are usually inferior to ASIC implementation. However, as the leading-edge technology is more rapidly adopted in field programmable gate array industry, and more ASIC-like dedicated functional blocks are integrated nowadays, the overall density and performance disadvantages are mitigated in modern high-end field programmable gate arrays. The integration of such dedicated blocks marks the transition from homogeneous architecture to heterogeneous. Consequently due to the shift to the heterogeneous architecture, it is desirable to optimize the economy of space on an integrated circuit chip with a more efficient method and system for the placement of heterogeneous blocks.